IMAGE SENSOR SOLUTIONS
Register Set (continued)
Register Name
Address
Mnemonic
Type
Reset Value
Main Configuration 1
03 Hex
MCFG1
Read/Write
00 Hex
Register Name
Address
Mnemonic
Type
Reset Value
Power Control Register 1
04 Hex
PCR
Read/Write
00 Hex
7
Bit
Bit Symbol
ColorMode
Description
Set when using a monochrome
sensor. When this bit is at a
logic 1, Sub-Sampling is set to
2:1 and every other row is read
out during interlace readout-
mode. Clear (the default) when
using a color sensor. When this
bit is at logic 0, sub-sampling is
Bit
7:4
3
2:1
Bit Symbol
PwdnPGA
PwdnGA
Description
Reserved
Assert to power down the pro-
grammable video gain amplifier.
Clear (the default) to power up the
video gain amplifiers.
Assert (11) to power down the pro-
set to 4:2 and every other row
pair is read out during interlace
mode.
[1:0]
grammable color gain amplifiers.
Clear (00, the default) to power up
the analog gain amplifiers.
6
ScanMode
Set to configure the sensor to
0
PwDnADC
Assert to power down the 12 bit
operate in interlace readout
mode. Clear (the default) to set
the sensor to operate in pro-
analog to digital convertor. Clear
(the default) to power up the 12 bit
analog to digital convertor.
gressive scan read out mode.
Register Name
Hclk Generator Register
5
HSubSamEn
Set to enable horizontal sub-
sampling. Clear (the default) to
disable horizontal sub-sampling.
Address
Mnemonic
Type
Reset Value
05 Hex
VCLKGEN
Read/Write
04 Hex.
NOTE: When horizontal sub-
sampling is enabled Pclk is
divided by 2. The Hsync active
time is the same in both sub-
sampled and non sub-sampled
mode. Therefore frame rate
does not increase with horizon-
tal sub-sampling.
Bit
7:6
Bit Symbol
PumpClkGen
Description
Use to divide the frequency of
the sensors master clock input,
mclk to generate the internal
charge pump clock, PumpClk as
shown in the table below .
4
3
VSubSamEn
Assert to enable vertical sub-
sampling. Clear (the default) to
disable vertical sub-sampling.
Reserved
00
01
10
11
PumpClk = mclk
PumpClk = mclk /2
PumpClk = mclk/4
PumpClk = mclk/8
2
SlaveMode
Use to configure the digital
5
Reserved
video port’s synchronisation sig-
1:0
nal to operate in slave mode. By
default the digital video’s port’s
synchronization signals are con-
figured to operate in master
mode.
Reserved
4:0
HclkGen
Use to divide the frequency of
the sensors master clock input,
mclk to generate the internal
sensor clock, Hclk.
Program 00 Hex (the default) for
Hclk to equal mclk or divide
mclk by any number between 1
and 31.
www.kodak.com/go/imagers 585-722-4385
29
Email:imagers@kodak.com
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